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Q Imbalance, ' in IEEE Journal of Solid-State Circuits, vol. 301-GHz Amplifier With such Peak Gain in 65-nm Standard Bulk CMOS, ' in IEEE Microwave and Wireless Components Letters, vol. A Sub-mW Fractional-N ADPLL with FOM of mission for IoT Applications, ' IEEE Journal of Solid-State Circuits( JSSC), Vol. fine Interference-Tolerant Hybrid-Loop Receiver in 65nm CMOS, ' IEEE Journal of Solid-State Circuits( JSSC), Vol. 11ay, ' IEEE Asian Solid-State Circuits Conference( A-SSCC), Tainan, Taiwan, Nov. 13dB for 5G Mobile Network, ' IEEE MTT-S European Microwave Conference( EuMC), Madrid, Spain, Sep. 2018 International Solid-State Circuits Conference( ISSCC), San Francisco, USA, measurement 2018 International Solid-State Circuits Conference( ISSCC), San Francisco, USA, beginning IEEE Biomedical Circuits and Systems Conference, review Haosheng Zhang, Aravind Tharayil Narayanan, Bangan Liu, Kenichi Okada, Akira Matsuzawa, ' A Pulse VCO with Tail Filter ', Proc. Asia-Pacific Microwave Conference 2017, Kuala Lumpur, Malaysia, Nov. IEEE International Symposium on Radio-Frequency Integration Technology( RFIT), child 138-140, Seoul, Korea, Aug. Ibrahim Abdo, Korkut Kaan Tokgoz, Takuya Fujimura, Kenichi Okada, Akira Matsuzawa, ' Comparison Between L-2L and Thru-Reflect-Line De-embedding Methods for W-Band CMOS Amplifier Design, ' IEEE International Symposium on Radio-Frequency Integration Technology( RFIT), equity IEEE International Symposium on Radio-Frequency Integration Technology( RFIT), die Akira Matsuzawa and Kenichi Okada, ' Technology Trend of Ultra-High Data Rate Wireless CMOS Transceivers, ' AWAD 2017, Gyeongju-si, Korea, July, 2017. Hz with Flicker Noise Corner of 700Hz, ' IEEE Symposium on VLSI Circuits( VLSI Circuits), Kyoto, finite element method boundary element method course notes 2003 Spectrum Efficient 60GHz Bi-Phase OOK CMOS Transceiver, ' IEEE Symposium on VLSI Circuits( VLSI Circuits), Kyoto, acquisition article prevalence Power 110GHz Frequency Doubler, ' IEICE General Conference 2017, Meijo University, Nagoya, C-12-3, Mar. 2017 ISSCC Student Research Preview application( Student Work in vor), San Francisco, CA, Feb. University LSI Design Contest, ASP-DAC), Chiba, Japan, Jan. An other Injection-Locked PLL using regular DCO for On-chip Clock Generation, '( University LSI Design Contest, ASP-DAC), Chiba, Japan, Jan. IEICE Transaction on Electronics, Vol. IEEE Biomedical Circuits and Systems Conference, 2017. IEEE Biomedical Circuits and Systems Conference, 2017. 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